--
-- VHDL Architecture Fietscomputer_lib.rxd_receiver.v
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp6241)
--          at - 12:49:46  9-04-2009
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY s_rxd_receiver IS
  PORT( 
  rxd   : IN     STD_LOGIC  := '1';
  clk   : IN     STD_LOGIC;
  rst   : IN     STD_LOGIC;
  data  : BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
  strb  : OUT    STD_LOGIC;
  rcv   : OUT    STD_LOGIC
  );
END ENTITY s_rxd_receiver;

--
ARCHITECTURE v OF s_rxd_receiver IS

SIGNAL q1, q0 : STD_LOGIC;


TYPE statetype IS (PU, Shift, EOC );
SIGNAL state : statetype;

SIGNAL cntr: INTEGER RANGE 0 TO 1023;

BEGIN
  
  
  PROCESS(rst, clk)
    BEGIN
      IF rst = '1' THEN
        q1 <= '1';
        q1 <= '1';
      ELSIF RISING_EDGE(clk) THEN
        
        q1 <= rxd;
        q0 <= q1;
        
      END IF;
    END PROCESS;
    
    
    
    
    
    PROCESS(rst, clk)
      BEGIN
        IF rst = '1' THEN
          data  <=  x"00";
          cntr  <= 0;
          state <= PU;
        ELSIF RISING_EDGE(clk) THEN
            
            CASE state IS
              
            WHEN PU =>
              cntr <= 0;
              IF q0 = '0'  THEN   
                state <= Shift;
              END IF;
              
              
            WHEN Shift =>
              cntr <= cntr + 1;
              CASE cntr IS
              WHEN 156 | 260 | 364 | 468 | 573 | 677 | 781 | 885 =>
                data <= rxd & data(7 DOWNTO 1);
              WHEN 989 =>   --0.989583
                state  <= EOC;
              WHEN OTHERS =>
                NULL;
              END CASE;
              
            WHEN EOC => 
              state <= pu;
              
               
              
            END CASE; 
            
            
            
            
        END IF;
      END PROCESS;
      
      
      strb <= '1' WHEN state = EOC   ELSE '0'; 
      
      rcv  <= '1' WHEN state = shift ELSE '0'; 
      
      
      
      
      
    END ARCHITECTURE v;
    
    
    
    
    
    